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NCP5680
the 200 ms time out can be activated by forcing the TPLGT
bit to high in the CONFIG0 register. The Picture Light
cannot be combined with a power flash pulse.
NTC Sensor
The external NTC element is controlled by the ENTC bit
in the CONFIG0 register. When the function is activated,
the external NTC element is biased by a programmable
constant current (in the 10 m A to 630 m A range), the voltage
developed across the NTC pin and GND being compared
to the reference voltage stored into the NTCREG register.
When the NTC voltage drops below the minimum level
(setup by the NTCREG register), the charge is de ? activated
and both the flash and the torch mode are automatically
switched OFF, reducing the power dissipated into the LED
to almost zero. The associated flip flop is reset to the
normal mode when a power OFF/ON sequence is forced,
or by pulsed Hi/Lo the NTCREG[CNTC] bit. In both case,
the NTC temperature must be cool enough to enable the
power current flow into the LED.
Time Out Security
When an extra security is requested by the end
application, and external structure shall be implemented to
handle the worst but rare case condition, i.e. when the
NCP5680 built ? in timer and time out fail simultaneously.
To handle such conditions, an external circuit will switch
off the two NMOS transistor when the time extend the
maximum 200 ms time out defined by the passive
component. There is no software associated with the
security circuit, the activation being automatically done
when any of the two NMOS is used to generate a power
flash pulse. The typical circuit is depicted in Figure 21.
DSTM1
S1
Implementation = /POR
1
2
U3A
3
1
2
74HC132
U4A
3
74HC08
DSTM2
S1
Implementation = NMOS
C1
1n
R1
100k
12
13
U4D
74HC132
11 Run
V
4
TimeMax 5 U4B
74HC132
6
Time ? Out
V
V
8
U4C
9
10
R2
1000k
D1
D1N4148
74HC132
C2
100n
Figure 21. Basic External Hardware Time Out Security Circuit
The NMOS signal is derived from the gate drive voltage
applied to the external NMOS transistor: this signal is fully
synchronized with a photo flash pulse. The positive going
slope generates a negative pulse at the RESET input of the
flip flop built with two NAND gate which, in turn, activates
the delay built with the RC network connected to a single
inverter. The flip ? flop is set when the RC timing ends (a
negative going pulse is present at the SET input), turning
ON the external NMOS transistor which, in turn, will force
to ground the gate of the power transistor. At this point, the
ILED current is disconnected and no more power is
new photo flash sequence, or using any kind of MCU
controlled signal.
I2C Protocol
The NCP5680 is considered as a Slave system, with no
possibility to take control of the bus, programmed by
means of the standard I2C protocol driven by the external
MCU. In addition, the internal STATUS register can be
read back upon request coming from the external MCU.
To program one particular register, the communication
takes place with three serial bytes:
dissipated in the circuit. To flip flop is reset by sending a
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